The present invention relates to digital processing. The present invention finds particular application in tomographic image reconstruction and will be described with particular reference thereto. However, it is to be appreciated that the invention is also applicable to other types of image and data processing.
In the field of computerized tomographic scanners, the accurate reconstruction of images is of utmost importance. One of the major drawbacks in accurate image reconstruction has been the amount of time necessary to complete the image reconstructions for each scan of a multi-scan procedure. The longer the time necessary to complete the image and initiate the next scan of the procedure, the more likely procedure degrading occurrences, such as patient movement, become.
Improving the speed of data acquisition or once data has been acquired, increasing the speed at which it is manipulated increases the speed of reconstruction of the scanned image. Central to the reconstruction of an image is a convolution process which prepares the data for backprojection into image. The speed of the convolution process is a constraint on the speed of the total system. Faster convolution achieves faster image reconstruction allowing for more accurate scans and less scans which must be re-performed.
In the past, array processor design used in CT scanning normally used a random access structure with single port, thereby allowing only a single memory location to be accessed in one clock cycle. This caused significant bottle necks in the transfer of data to the arithmetic unit. Additionally, array processors previously used contained significant amounts of unused clock cycles in transferring of data. Therefore, for the above two reasons, the arithmetic unit operated far below its possible theoretical maximum. This in turn significantly slowed down the entire image reconstruction process.
The present invention provides a convolution technique and circuit that improves convolution processing speed.